(a) Field of the Invention
The present invention relates to a semiconductor device having a through-hole of a two-level structure and, more particularly, to an electrode structure for a stacked capacitor of a memory cell in a semiconductor memory device.
(b) Description of the Related Art
Dynamic random access memory (DRAM) has a stacked capacitor in each memory cell for storing data thereon. FIG. 1 shows the structure of a stacked capacitor in a conventional memory cell, which is fabricated by a known process as described below. First, a field oxide film 102 of an about 400 nm thickness is formed by a LOCOS technology on a p-conductivity type silicon substrate 101 to define an array of cell areas. Subsequently, a gate oxide film (not shown), gate electrode (not shown) and source/drain regions 103 of a MOSFET are formed in each cell area, followed by deposition of a BPSG (borophospho-silicate glass) film 104 as an interlevel dielectric film having a thickness of about 1000 nm and deposition of a SiO.sub.2 film 105 having a thickness of about 200 nm. Thereafter, a through-hole 106 of a 0.3 .mu.m.times.0.3 .mu.m cross-section is formed in the BPSG film 104 and the SiO.sub.2 film 105 in each cell region to expose a part of the source/drain region 103. Then, a phosphorous (P)-doped amorphous silicon 107 is deposited on the entire surface including inside the through-hole 106 to a thickness of about 500 nm, followed by patterning thereof to form a capacitor electrode, or bottom electrode of a stacked capacitor.
In the design of the cell structure as described above, the alignment margin between the through-hole 106 and the bottom electrode 107 has been reduced down to as low as 0.05 .mu.m with the development of a higher integration of the DRAM. In FIG. 1, there is shown an ideal case of the alignment wherein no misalignment is present between the through-hole 106 and the bottom electrode 107. However, a critical misalignment is sometimes involved in the DRAM, as shown in FIG. 2A, wherein the misalignment is larger than the design margin L1. In such a case, the bottom electrode 107 exposes the SiO.sub.2 film 105 and the BPSG film 104 within the through-hole 106.
Back to FIG. 1, the patterning of the bottom electrode 107 is generally followed by a pre-treatment in which a natural oxide film is removed from the surface of the bottom electrode 107 by using a dilute hydrof luoric acid before the subsequent step of deposition of a nitride film acting as a capacitor film, or insulator film of the capacitor. In this step, the etching rate by the dilute hydrofluoric acid is as low as about 200 angstroms/minute in the SiO.sub.2 film as compared to about 600 angstroms/minute in the BPSG film.
In addition, it takes above five minutes to entirely remove the natural oxide film by the etching, and accordingly, as shown in FIG. 2B, the BPSG film 104 is additionally etched by a significant amount in the through-hole 106. Similar problem occurs in the step of formation of a hemispherical grain (HSG) structure for the capacitor electrode. In the process for fabrication of the HSG structure, the etching step for natural oxide film is generally effected on the capacitor electrode by using a dilute hydrof luoric acid, which also involves a situation similar to etching of the BPSG film.
To overcome the above problem, it is proposed that an oxide spacer film be formed on the side wall of the through-hole for protection of the BPSG film, as shown in FIG. 3A. In this proposal, a SiO.sub.2 film 108a as low as about 100 nm-thick is formed after the through-hole 106 is formed in a SiO.sub.2 film 105 and the BPSG film 104 for exposing the surface of the source/drain region 103. The SiO.sub.2 film 108a is then etched-back to be left in the through-hole 106 as a side-wall film 108, followed by deposition of a P-doped amorphous silicon layer to a thickness of about 500 nm and patterning thereof to form a bottom electrode 107 in the through-hole 106, as shown in FIG. 3B. In this technique, the alignment margin L1 between the through-hole 106 and the bottom electrode 107 is increased by an amount corresponding to the thickness (0.1 .mu.m) of the side wall 108, thereby avoiding the etching of the BPSG film 104 even if a significant misalignment occurs between the bottom electrode 107 and the through-hole 106.
In the proposal as mentioned above, however, the side-wall film 108 generally suffers from a poor step coverage problem and variation of the film thickness of the side wall due to the high aspect ratio of the through-hole 106 in a higher integrated circuit. The poor step coverage and the variation of the film thickness necessitates a marginal etching of the side-wall film for exposing the silicon surface, which sometimes involves an over-etching of the silicon surface as illustrated in FIG. 3B to cause a leakage current at the junction in the silicon substrate 101.
Patent Publication JP-A-2(1990)-170561 describes a similar technique wherein two-level interconnection system has a side-wall film in a through-hole which connects upper and lower level interconnect layers together.
Patent Publication JP-A-3-174766 proposes an improvement of the aspect ratio, such as shown in FIG. 4, by providing a two-layer insulation structure, wherein two through-holes for receiving a polysilicon plug 205 and a polysilicon electrodes 208 and formed in SiO.sub.2 films 204 and 206, respectively, are communicated to each other to define a substantially single capacitor electrode.
In the described two-layer insulation structure, although the aspect ratio of the through-hole can be improved, the alignment margin between the capacitor electrode and the through-hole cannot be improved. Moreover, it raises costs of the memory device due to the increased fabrication step for photolithography.